Type aliases
CodeListingMap
CodeListingMap: {}
FileData
FileData: string | Uint8Array
Segment
Segment: { last?: number; name: string; size: number; start: number; type?: string }
Type declaration
-
Optional last?: number
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name: string
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size: number
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start: number
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Optional type?: string
VerilogOutput
VerilogOutput: { code: string; name: string; ports: any[]; program_rom: Uint8Array; program_rom_variable: string; signals: any[] }
Type declaration
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code: string
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name: string
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ports: any[]
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program_rom: Uint8Array
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program_rom_variable: string
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signals: any[]
WorkerResult