Indexed-Indirect Mode – (Indirect + X)¶

Syntax¶

instruction (base_pointer, X)

Description¶

In the indexed-indirect addressing mode, the effective address is calculated by adding the contents of the X register to the base_pointer. The result is a zero-page address, which points to the low byte of the actual target address. The high byte of the target address is stored in the next consecutive zero-page location.

The processor then fetches the 16-bit address from these two zero-page locations, and the instruction operates on the memory location pointed to by this 16-bit address.

Example¶

Here’s an example using the LDA instruction in indexed-indirect addressing mode:

LDA ($20,X)

Assume that the X register contains $04, and the memory locations $24 through $25 has the following contents:

$20: $10
$21: $80

The instruction will perform the following steps:

Add the X register ($04) to the base_pointer ($20), resulting in the zero-page address $24.
Fetch the low byte of the target address from $24 ($10).
Fetch the high byte of the target address from $25 ($80).
Combine the high and low bytes to form the target address: $8010.
Load the value at memory location $8010 into the accumulator.

Use Cases¶

Indexed-indirect addressing mode is particularly useful for implementing jump tables, also known as branch tables, in assembly language. This technique allows for efficient branching based on the contents of a register, such as the X register. It can also be used for accessing elements in an array or a data structure using an index.

Bugs¶

One known bug with the 6502 indexed-indirect addressing mode is the “page crossing bug”. When the sum of the base_pointer and the X register results in a carry from the zero-page to the next memory page, the processor does not account for this carry. The effective address will be truncated to the range $00 to $FF. Be aware of this limitation when working with indexed-indirect addressing mode.

Instructions Supported¶

Syntax	Bytes	Cycles
ORA (zp,x)	`01 nn`	6
AND (zp,x)	`21 nn`	6
EOR (zp,x)	`41 nn`	6
ADC (zp,x)	`61 nn`	6
STA (zp,x)	`81 nn`	6
LDA (zp,x)	`A1 nn`	6
CMP (zp,x)	`C1 nn`	6
SBC (zp,x)	`E1 nn`	6

Undocumented Instructions¶

Syntax	Bytes	Cycles
+SLO (zp,x)	`03 nn`	8
+RLA (zp,x)	`23 nn`	8
+SRE (zp,x)	`43 nn`	8
+RRA (zp,x)	`63 nn`	8
+SAX (zp,x)	`83 nn`	6
+LAX (zp,x)	`A3 nn`	6
+DCP (zp,x)	`C3 nn`	8
+ISB (zp,x)	`E3 nn`	8