Posts tagged riscv
RISC-V in Your Browser with Verilog
- 08 November 2025
RISC-V is the fifth generation of an open CPU architecture with its roots in academia. Now that it is headed for ISO/IEC standardization, it’s attracting more interest.
One nice thing about the RISC-V instruction set is its modularity. There are 32-bit and 64-bit instruction sets, each with a full and compact version. The base instruction sets are very basic; even multiplication and division are provided in an optional extension.
We can easily run the FemtoRV32 Verilog implementation in 8bitworkshop. This gives us a basic RV32I (32-bit integer) instruction set that we can use in projects.