# 3.7.2 Release¶

A minor update with some bug fixes and some new features.

## VCS and DASM¶

Added better support for ca65 assembler, though DASM is probably still the better choice for VCS programming. DASM has better parsing of macros (you can step through them in the debugger) and improved error messages.

Improved cycle analysis tool that counts up to 76*4 scanlines and properly inspects JSR subroutines.

KIL ($02) instruction breaks into debugger – you can use this to implement assertions, for example. ## Verilog¶ The Verilog platform now supports 32-bit RGB output as long as the upper 8 bits are set ($FFbbggrr)

If you load a lone module (i.e. with no CRT output) you can toggle or set its input signals by clicking on the Scope view.

## Experimental Languages¶

Experimental support for Wiz, a “high-level assembly language” that lets you write expressions but still requires you to be aware of CPU registers. There are a few examples for Atari 2600, NES, and MSX.

Experimental support for Silice, a semi-procedural HDL. It’s fairly slow to simulate in the IDE, because it generates Verilog that tends to be bulkier than hand-coded Verilog. (It’d be great to have an HDL which is performant when translated to JavaScript, then you could use it to write emulators for the IDE!)