ORA (zp,X)

Mode

Syntax

Bytes

Cycles

Indirect,X

ORA ($nn,X)

01 nn

6

The “ORA (zp,X)” instruction in the 6502 microprocessor performs a bitwise OR operation between the accumulator (A) and the contents of the memory address specified by the indirect addressing mode. It updates the zero (Z) and negative (N) flags in the status register according to the result of the operation. The indirect addressing mode is achieved by taking the zero page address (zp), adding the X index register’s value, and using the resulting 8-bit address to fetch the effective 16-bit address.

Here’s an explanation of what happens during each cycle of the “ORA (zp,X)” instruction:

  1. The program counter (PC) is incremented to fetch the zero page address (zp) from the memory.

  2. The fetched zero page address (zp) is stored in the address register (AD), and the AD is set to the value of (zp).

  3. The value of the X register is added to the zero page address (zp) stored in AD, and the result is truncated to 8 bits (effectively wrapped around within the zero page). The AD is set to the new calculated address.

  4. The least significant byte (LSB) of the effective 16-bit address is fetched by incrementing the address in AD by 1 (wrapped around the zero page), and the AD is set to the fetched LSB value.

  5. The most significant byte (MSB) of the effective 16-bit address is fetched from memory, and the AD is set to the complete 16-bit address by combining the MSB and the previously fetched LSB.

  6. The value at the effective 16-bit address is fetched from memory and bitwise OR’d with the accumulator (A). The zero (Z) and negative (N) flags are updated based on the result of the operation. Finally, the next opcode byte is fetched, preparing for the next instruction.

In summary, the “ORA (zp,X)” instruction performs a bitwise OR operation between the accumulator and the memory contents at an effective 16-bit address, which is determined by the zero page address, the X index register, and indirect addressing. The zero (Z) and negative (N) flags are updated based on the result.

The ORA (zp,X) instruction performs a logical OR operation between the contents of the accumulator (A) and the value stored in memory at the zero-page address that is computed by adding the X register to a zero-page address byte operand. The instruction takes 6 CPU cycles to complete.

Here’s what happens on each cycle:

  1. Opcode Fetch. The CPU fetches the opcode from memory and increments the program counter (PC) by 1.

  2. Zero-Page Address Fetch. The CPU reads the zero-page address byte from memory pointed to by the updated PC and stores it in the address register (AD).

  3. Compute Zero-Page Address. The CPU adds the value of X register to the address byte in the AD register, wrapping around if the result exceeds $FF. The resulting address is stored back in the AD register.

  4. Fetch Indirect Address Low Byte. The CPU reads the low byte of the 16-bit address from the zero-page address in the AD register and increments the AD register to point to the next byte of memory.

  5. Fetch Indirect Address High Byte. The CPU reads the high byte of the 16-bit address from the next byte of memory pointed to by the incremented AD register.

  6. OR Operation. The CPU reads the byte of data from memory at the address computed in cycles 4 and 5 and performs a logical OR operation with the contents of the accumulator (A), storing the result back in the accumulator (A). The CPU updates the N and Z flags based on the new value of A. The opcode fetch for the next instruction is also initiated by the CPU.

See the ORA instruction for more details.

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